
RealtimeAudioController.elf:     file format elf32-avr

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         000001f2  00000000  00000000  00000074  2**1
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .bss          00000322  00800100  00800100  00000266  2**0
                  ALLOC
  2 .stab         000006cc  00000000  00000000  00000268  2**2
                  CONTENTS, READONLY, DEBUGGING
  3 .stabstr      00000090  00000000  00000000  00000934  2**0
                  CONTENTS, READONLY, DEBUGGING
  4 .debug_aranges 00000020  00000000  00000000  000009c4  2**0
                  CONTENTS, READONLY, DEBUGGING
  5 .debug_pubnames 00000056  00000000  00000000  000009e4  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_info   00000197  00000000  00000000  00000a3a  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_abbrev 0000010a  00000000  00000000  00000bd1  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_line   000002fd  00000000  00000000  00000cdb  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_frame  00000040  00000000  00000000  00000fd8  2**2
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_str    00000127  00000000  00000000  00001018  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    0000019b  00000000  00000000  0000113f  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_pubtypes 0000002b  00000000  00000000  000012da  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_ranges 00000018  00000000  00000000  00001305  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000000 <__vectors>:
   0:	0c 94 34 00 	jmp	0x68	; 0x68 <__ctors_end>
   4:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
   8:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
   c:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  10:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  14:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  18:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  1c:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  20:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  24:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  28:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  2c:	0c 94 ed 00 	jmp	0x1da	; 0x1da <__vector_11>
  30:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  34:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  38:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  3c:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  40:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  44:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  48:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  4c:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  50:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  54:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  58:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  5c:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  60:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>
  64:	0c 94 46 00 	jmp	0x8c	; 0x8c <__bad_interrupt>

00000068 <__ctors_end>:
  68:	11 24       	eor	r1, r1
  6a:	1f be       	out	0x3f, r1	; 63
  6c:	cf ef       	ldi	r28, 0xFF	; 255
  6e:	d4 e0       	ldi	r29, 0x04	; 4
  70:	de bf       	out	0x3e, r29	; 62
  72:	cd bf       	out	0x3d, r28	; 61

00000074 <__do_clear_bss>:
  74:	14 e0       	ldi	r17, 0x04	; 4
  76:	a0 e0       	ldi	r26, 0x00	; 0
  78:	b1 e0       	ldi	r27, 0x01	; 1
  7a:	01 c0       	rjmp	.+2      	; 0x7e <.do_clear_bss_start>

0000007c <.do_clear_bss_loop>:
  7c:	1d 92       	st	X+, r1

0000007e <.do_clear_bss_start>:
  7e:	a2 32       	cpi	r26, 0x22	; 34
  80:	b1 07       	cpc	r27, r17
  82:	e1 f7       	brne	.-8      	; 0x7c <.do_clear_bss_loop>
  84:	0e 94 50 00 	call	0xa0	; 0xa0 <main>
  88:	0c 94 f7 00 	jmp	0x1ee	; 0x1ee <_exit>

0000008c <__bad_interrupt>:
  8c:	0c 94 00 00 	jmp	0	; 0x0 <__vectors>

00000090 <signal_error>:
#define signal_more_data_on() (PORTB |= (1 << PB1))
#define signal_more_data_off() (PORTB &= ~(1 << PB1))

volatile uint16_t error_time = 0;
void signal_error() {
	error_time = 60000;
  90:	80 e6       	ldi	r24, 0x60	; 96
  92:	9a ee       	ldi	r25, 0xEA	; 234
  94:	90 93 01 01 	sts	0x0101, r25
  98:	80 93 00 01 	sts	0x0100, r24
	error_led_on();
  9c:	45 9a       	sbi	0x08, 5	; 8
}
  9e:	08 95       	ret

000000a0 <main>:

//uint16_t buf_pos_read = 0;
uint8_t buffer[2][BUFFER_SIZE];

int main(void)
{
  a0:	ff 92       	push	r15
  a2:	0f 93       	push	r16
  a4:	1f 93       	push	r17
  a6:	cf 93       	push	r28
  a8:	df 93       	push	r29
	setup_error_led();
  aa:	3d 9a       	sbi	0x07, 5	; 7
	error_led_off();
  ac:	45 98       	cbi	0x08, 5	; 8
	setup_signal_more_data();
  ae:	21 9a       	sbi	0x04, 1	; 4
	signal_more_data_on();
  b0:	29 9a       	sbi	0x05, 1	; 5
#define signal_more_data_on() (PORTB |= (1 << PB1))
#define signal_more_data_off() (PORTB &= ~(1 << PB1))

volatile uint16_t error_time = 0;
void signal_error() {
	error_time = 60000;
  b2:	80 e6       	ldi	r24, 0x60	; 96
  b4:	9a ee       	ldi	r25, 0xEA	; 234
  b6:	90 93 01 01 	sts	0x0101, r25
  ba:	80 93 00 01 	sts	0x0100, r24
	error_led_on();
  be:	45 9a       	sbi	0x08, 5	; 8
  c0:	e2 e0       	ldi	r30, 0x02	; 2
  c2:	f1 e0       	ldi	r31, 0x01	; 1
  c4:	a2 e9       	ldi	r26, 0x92	; 146
  c6:	b2 e0       	ldi	r27, 0x02	; 2
	signal_error();
	
	//init buffers
	int i = 0;
	for (i = 0; i < BUFFER_SIZE; i++) {
		buffer[0][i] = 0x100/2;
  c8:	80 e8       	ldi	r24, 0x80	; 128
  ca:	81 93       	st	Z+, r24
		buffer[1][i] = 0x100/2;
  cc:	8d 93       	st	X+, r24
	
	signal_error();
	
	//init buffers
	int i = 0;
	for (i = 0; i < BUFFER_SIZE; i++) {
  ce:	92 e0       	ldi	r25, 0x02	; 2
  d0:	e2 39       	cpi	r30, 0x92	; 146
  d2:	f9 07       	cpc	r31, r25
  d4:	d1 f7       	brne	.-12     	; 0xca <main+0x2a>
	
	//left - D6, A
	//right -D5, B
	
	//setup pwm
	DDRD |= (1 <<DDD6) | (1 << DDD5);
  d6:	8a b1       	in	r24, 0x0a	; 10
  d8:	80 66       	ori	r24, 0x60	; 96
  da:	8a b9       	out	0x0a, r24	; 10
	TCCR0A = (1 << COM0A1) | (1 << COM0B1) |	//Non Inverting
  dc:	83 ea       	ldi	r24, 0xA3	; 163
  de:	84 bd       	out	0x24, r24	; 36
			 (1 << WGM00) | (1 << WGM01);		//Fast Pwm Mode
	TCCR0B = (1 << CS00);						//Clock as source
  e0:	81 e0       	ldi	r24, 0x01	; 1
  e2:	85 bd       	out	0x25, r24	; 37
	
	//setup spi - CPOL = 0, CPHA = 0, Mode = Slave
	SPCR = (1 << SPE); //(1 << SPIE) | 
  e4:	90 e4       	ldi	r25, 0x40	; 64
  e6:	9c bd       	out	0x2c, r25	; 44
	//create interrupt on slave select - no longer needed
	///PCMSK0 = (1 << PCINT2);				
	///PCICR = (1 << PCIE0);
	
	//setup audio output interrupt
	TCCR1B = (1 << WGM12) |		//CTC mode with A as Top
  e8:	99 e0       	ldi	r25, 0x09	; 9
  ea:	90 93 81 00 	sts	0x0081, r25
			 (1 << CS10);		//Freq of main oscillator
	TCNT1H = 0;					//Start clock at 0
  ee:	10 92 85 00 	sts	0x0085, r1
	TCNT1L = 0;
  f2:	10 92 84 00 	sts	0x0084, r1
	OCR1AH = 0x1;				//Set to a value of 454 - 1 
  f6:	80 93 89 00 	sts	0x0089, r24
	OCR1AL = 0xC6 - 1;			//to create an interrupt freq of ~44.1khz
  fa:	85 ec       	ldi	r24, 0xC5	; 197
  fc:	80 93 88 00 	sts	0x0088, r24


	uint8_t* read_pos = 0;
	uint8_t read_remaining = 0;

	uint8_t cur_buf_read = 0;
 100:	00 e0       	ldi	r16, 0x00	; 0
	uint8_t* write_pos = 0;
	uint16_t write_size = 0;


	uint8_t* read_pos = 0;
	uint8_t read_remaining = 0;
 102:	10 e0       	ldi	r17, 0x00	; 0
	
	uint8_t* write_pos = 0;
	uint16_t write_size = 0;


	uint8_t* read_pos = 0;
 104:	e0 e0       	ldi	r30, 0x00	; 0
 106:	f0 e0       	ldi	r31, 0x00	; 0
	//Enable interrupts so the fun can begin
	//sei();
	
	
	uint8_t* write_pos = 0;
	uint16_t write_size = 0;
 108:	80 e0       	ldi	r24, 0x00	; 0
 10a:	90 e0       	ldi	r25, 0x00	; 0
	
	//Enable interrupts so the fun can begin
	//sei();
	
	
	uint8_t* write_pos = 0;
 10c:	c0 e0       	ldi	r28, 0x00	; 0
 10e:	d0 e0       	ldi	r29, 0x00	; 0
			if (write_size < BUFFER_SIZE / 2)
				signal_more_data_off();
		} else if (TIFR1 & (1 << OCF1A)) {		//Audio interrupt next highest priority
			
			//clear status flag
			TIFR1 = (1 << OCF1A);
 110:	22 e0       	ldi	r18, 0x02	; 2
 112:	f2 2e       	mov	r15, r18
				//sanity check for errors
				if (write_size != 0)
					signal_error();

				//begin filling old buffer with new data
				write_pos = buffer[cur_buf_read];
 114:	40 e9       	ldi	r20, 0x90	; 144
 116:	51 e0       	ldi	r21, 0x01	; 1
#define signal_more_data_on() (PORTB |= (1 << PB1))
#define signal_more_data_off() (PORTB &= ~(1 << PB1))

volatile uint16_t error_time = 0;
void signal_error() {
	error_time = 60000;
 118:	60 e6       	ldi	r22, 0x60	; 96
 11a:	7a ee       	ldi	r23, 0xEA	; 234

	uint8_t cur_buf_read = 0;
	
    while(1) {
		
		if (SPSR & (1 << SPIF)) {				//SPI interrupt highest priority
 11c:	0d b4       	in	r0, 0x2d	; 45
 11e:	07 fc       	sbrc	r0, 7
 120:	0f c0       	rjmp	.+30     	; 0x140 <main+0xa0>
			} else {
				SPDR;
			}
			if (write_size < BUFFER_SIZE / 2)
				signal_more_data_off();
		} else if (TIFR1 & (1 << OCF1A)) {		//Audio interrupt next highest priority
 122:	b1 9b       	sbis	0x16, 1	; 22
 124:	18 c0       	rjmp	.+48     	; 0x156 <main+0xb6>
			
			//clear status flag
			TIFR1 = (1 << OCF1A);
 126:	f6 ba       	out	0x16, r15	; 22
			
			//output data
			OCR0A = *read_pos++;
 128:	df 01       	movw	r26, r30
 12a:	2d 91       	ld	r18, X+
 12c:	27 bd       	out	0x27, r18	; 39
			OCR0B = *read_pos++;
 12e:	21 81       	ldd	r18, Z+1	; 0x01
 130:	28 bd       	out	0x28, r18	; 40
			read_remaining--;
 132:	11 50       	subi	r17, 0x01	; 1
			
			//load new buffer
			if (read_remaining == 0) {
 134:	51 f1       	breq	.+84     	; 0x18a <main+0xea>
			//clear status flag
			TIFR1 = (1 << OCF1A);
			
			//output data
			OCR0A = *read_pos++;
			OCR0B = *read_pos++;
 136:	fd 01       	movw	r30, r26
 138:	31 96       	adiw	r30, 0x01	; 1

	uint8_t cur_buf_read = 0;
	
    while(1) {
		
		if (SPSR & (1 << SPIF)) {				//SPI interrupt highest priority
 13a:	0d b4       	in	r0, 0x2d	; 45
 13c:	07 fe       	sbrs	r0, 7
 13e:	f1 cf       	rjmp	.-30     	; 0x122 <main+0x82>
			if (write_size > 0) {
 140:	00 97       	sbiw	r24, 0x00	; 0
 142:	09 f4       	brne	.+2      	; 0x146 <main+0xa6>
 144:	47 c0       	rjmp	.+142    	; 0x1d4 <main+0x134>
				*write_pos++ = SPDR;
 146:	2e b5       	in	r18, 0x2e	; 46
 148:	29 93       	st	Y+, r18
				write_size--;
 14a:	01 97       	sbiw	r24, 0x01	; 1
			} else {
				SPDR;
			}
			if (write_size < BUFFER_SIZE / 2)
 14c:	88 3c       	cpi	r24, 0xC8	; 200
 14e:	91 05       	cpc	r25, r1
 150:	28 f7       	brcc	.-54     	; 0x11c <main+0x7c>
				signal_more_data_off();
 152:	29 98       	cbi	0x05, 1	; 5
 154:	e3 cf       	rjmp	.-58     	; 0x11c <main+0x7c>
				else cur_buf_read = 0;
				read_pos = buffer[cur_buf_read];
				read_remaining = BUFFER_SIZE / 2;
			} 

		} else if (error_time > 0) {			//Error function lowest priority
 156:	20 91 00 01 	lds	r18, 0x0100
 15a:	30 91 01 01 	lds	r19, 0x0101
 15e:	21 15       	cp	r18, r1
 160:	31 05       	cpc	r19, r1
 162:	e1 f2       	breq	.-72     	; 0x11c <main+0x7c>
			error_time--;
 164:	20 91 00 01 	lds	r18, 0x0100
 168:	30 91 01 01 	lds	r19, 0x0101
 16c:	21 50       	subi	r18, 0x01	; 1
 16e:	30 40       	sbci	r19, 0x00	; 0
 170:	30 93 01 01 	sts	0x0101, r19
 174:	20 93 00 01 	sts	0x0100, r18
			if (error_time == 0)
 178:	20 91 00 01 	lds	r18, 0x0100
 17c:	30 91 01 01 	lds	r19, 0x0101
 180:	21 15       	cp	r18, r1
 182:	31 05       	cpc	r19, r1
 184:	59 f6       	brne	.-106    	; 0x11c <main+0x7c>
				error_led_off();
 186:	45 98       	cbi	0x08, 5	; 8
 188:	c9 cf       	rjmp	.-110    	; 0x11c <main+0x7c>
			
			//load new buffer
			if (read_remaining == 0) {
				
				//sanity check for errors
				if (write_size != 0)
 18a:	00 97       	sbiw	r24, 0x00	; 0
 18c:	29 f0       	breq	.+10     	; 0x198 <main+0xf8>
#define signal_more_data_on() (PORTB |= (1 << PB1))
#define signal_more_data_off() (PORTB &= ~(1 << PB1))

volatile uint16_t error_time = 0;
void signal_error() {
	error_time = 60000;
 18e:	70 93 01 01 	sts	0x0101, r23
 192:	60 93 00 01 	sts	0x0100, r22
	error_led_on();
 196:	45 9a       	sbi	0x08, 5	; 8
				//sanity check for errors
				if (write_size != 0)
					signal_error();

				//begin filling old buffer with new data
				write_pos = buffer[cur_buf_read];
 198:	80 2f       	mov	r24, r16
 19a:	90 e0       	ldi	r25, 0x00	; 0
 19c:	84 9f       	mul	r24, r20
 19e:	e0 01       	movw	r28, r0
 1a0:	85 9f       	mul	r24, r21
 1a2:	d0 0d       	add	r29, r0
 1a4:	94 9f       	mul	r25, r20
 1a6:	d0 0d       	add	r29, r0
 1a8:	11 24       	eor	r1, r1
 1aa:	ce 5f       	subi	r28, 0xFE	; 254
 1ac:	de 4f       	sbci	r29, 0xFE	; 254
				write_size = BUFFER_SIZE;
				signal_more_data_on();
 1ae:	29 9a       	sbi	0x05, 1	; 5
		
				//switch read buffer
				if (cur_buf_read == 0) cur_buf_read = 1;
 1b0:	81 e0       	ldi	r24, 0x01	; 1
 1b2:	01 11       	cpse	r16, r1
 1b4:	80 e0       	ldi	r24, 0x00	; 0
 1b6:	08 2f       	mov	r16, r24
				else cur_buf_read = 0;
				read_pos = buffer[cur_buf_read];
 1b8:	90 e0       	ldi	r25, 0x00	; 0
 1ba:	84 9f       	mul	r24, r20
 1bc:	f0 01       	movw	r30, r0
 1be:	85 9f       	mul	r24, r21
 1c0:	f0 0d       	add	r31, r0
 1c2:	94 9f       	mul	r25, r20
 1c4:	f0 0d       	add	r31, r0
 1c6:	11 24       	eor	r1, r1
 1c8:	ee 5f       	subi	r30, 0xFE	; 254
 1ca:	fe 4f       	sbci	r31, 0xFE	; 254
				read_remaining = BUFFER_SIZE / 2;
 1cc:	18 ec       	ldi	r17, 0xC8	; 200
				if (write_size != 0)
					signal_error();

				//begin filling old buffer with new data
				write_pos = buffer[cur_buf_read];
				write_size = BUFFER_SIZE;
 1ce:	80 e9       	ldi	r24, 0x90	; 144
 1d0:	91 e0       	ldi	r25, 0x01	; 1
 1d2:	a4 cf       	rjmp	.-184    	; 0x11c <main+0x7c>
		if (SPSR & (1 << SPIF)) {				//SPI interrupt highest priority
			if (write_size > 0) {
				*write_pos++ = SPDR;
				write_size--;
			} else {
				SPDR;
 1d4:	2e b5       	in	r18, 0x2e	; 46
			}
			if (write_size < BUFFER_SIZE / 2)
				signal_more_data_off();
 1d6:	29 98       	cbi	0x05, 1	; 5
 1d8:	a1 cf       	rjmp	.-190    	; 0x11c <main+0x7c>

000001da <__vector_11>:
	
}
*/

//44.1KHz timer interrupt
ISR(TIMER1_COMPA_vect) {
 1da:	1f 92       	push	r1
 1dc:	0f 92       	push	r0
 1de:	0f b6       	in	r0, 0x3f	; 63
 1e0:	0f 92       	push	r0
 1e2:	11 24       	eor	r1, r1


	
	
 1e4:	0f 90       	pop	r0
 1e6:	0f be       	out	0x3f, r0	; 63
 1e8:	0f 90       	pop	r0
 1ea:	1f 90       	pop	r1
 1ec:	18 95       	reti

000001ee <_exit>:
 1ee:	f8 94       	cli

000001f0 <__stop_program>:
 1f0:	ff cf       	rjmp	.-2      	; 0x1f0 <__stop_program>
